A frequency synthesizer creates multiple output signals, each with a different frequency, from a reference signal that has a highly stable reference frequency. The reference signal is generated by a crystal oscillator. Typically, a synthesizer comprises a voltage controllable oscillator (VCO) in a phase-locked-loop (PLL). The PLL controls the oscillator to keep the frequency and phase of the oscillator's output signal locked to those of the reference signal. The PLL has a phase detector to compare the phase of the oscillator's output signal with the phase of the reference signal. The detector controls a charge pump that supplies an error signal to the VCO in proportion to the phase difference detected. If the phase difference is zero, the pump provides a zero error signal. The PLL has a low-pass filter between the output of the pump and the control input of the VCO. The filter's task is to remove high-frequency contributions, e.g., noise, from the error signal that otherwise would modulate the VCO's frequency. If the bandwidth of the filter is made smaller, the PLL's noise performance is increased. However, lowering the bandwidth also increases the settling time that is needed for the PLL to lock in on the reference signal. Typically, the output frequency is divided by an integer factor N prior to carrying out phase comparison with the reference frequency. The division enables comparing frequencies that have similar values. The factor N can be made variable to provide a plurality of different output frequencies, e.g., for switching between channels in a communication device. The divider is usually implemented with a counter. Therefore, the factor N is an integer. The resolution in the divided output frequency equals the reference frequency. The resolution can be made finer by using a lower reference frequency. However, the error signal supplied by the phase detector follows then the detected phase difference more slowly. In addition, the low-pass filter then has to have a lower cut-off frequency that increases the settling time as mentioned above.
The fractional-N frequency synthesis provides a solution to this conflict between fine resolution and settling time. Frequency synthesizers with a PLL and a fractional-N division are discussed in, e.g., U.K. patent 1,560,233 and in "Fractional-N PLL Provides Fast, Low-Noise Synthesis", Wing S. Djen and Daniel Linebarger, Microwaves & RF, May 1994. Fractional-N division generates an output frequency whose ratio with the reference frequency is not an integer. A programmable frequency divider is located between the VCO and the phase detector, and the divide factor is switched between N and N+1 on a proportion x of the VCO's cycles giving on the average a division ratio close to N+x. Fractional-N division in a frequency synthesizer helps to obtain a good frequency resolution, which is specially important in digital cellular standards.
The fractional divide process causes variations in the period of the waveform at the output of the programmable divider. Division by N+1 requires one more input cycle than dividing by N. The result is a periodic phase error that causes corresponding side bands (fractional spurs) in the VCO's output spectrum. In other words, the output of the divider is modulated with a fractional phase ripple as a result of the periodically changing division ratios. This ripple causes phase jitter in the VCO's output signal. This jitter is the short-term variations of the significant instants of the VCO's output signal from their ideal positions in time.
U.K. patent 1,560,233, mentioned above and herewith incorporated by reference, teaches mitigating the jitter effects using voltage compensation. An analog compensation voltage is generated, which is added to the output voltage of the phase comparator at the input of the loop filter. This is achieved as follows. The known synthesizer comprises an accumulator whose capacity is referred to as fractional modulus and whose content gets increased by a certain fractional increment every time the programmable divider supplies an output pulse. Assume that the accumulator is set to zero. Every N cycles of the VCO the divider supplies an output pulse in response to which the fractional increment is being added to the content of the accumulator. When the accumulator overflows, i.e., has reached the fractional modulus, the dividing factor is changed to N+1. The dividing factor is reset to N after the divider has supplied its next output pulse. Accordingly, the fraction x is equal to the reciprocal of the integer number of times the fractional increment fits into the fractional modulus. Although, on the average, the frequency division by a factor N+x is correct, the instantaneous phase of the VCO's output signal is not constant. The input to the phase detector representing the VCO's output signal divided by N advances on the reference signal and produces a ramp error in the phase difference. This ramp causes the jitter at the VCO's output. The content of the accumulator is proportional to this phase difference and, if scaled properly, converted to a voltage and subtracted from the error signal supplied by the phase detector, compensates to some degree for the jitter.
Low-voltage 2GHz fractional-N synthesizer SA8025A of Philips Semiconductors, a division of Philips Electronics N.V., uses fractional current compensation. See Philips Semiconductors Data Handbook IC-17, 1996 for more details. The induced jitter is considered an amount of charge Q.sub.JITTER taken from the low-pass filter and proportional to: EQU Q.sub.JITTER .varies.I.sub.PUMP /[F.sub.VCO *F.sub.MOD ], (1)
wherein: I.sub.PUMP is the value of the main charge pump current; F.sub.VCO is the VCO's frequency, and FMOD is the fractional modulus (a dimensionless quantity). Compensation is achieved by supplying a compensation charge Qcomp timed by the reference frequency FREF according to the proportionality relationship: EQU Q.sub.COMP .varies.I.sub.COMP /F.sub.REF, (2)
wherein I.sub.COMP is the magnitude of the compensation current. Combining expressions (1) and (2) gives as a result for the compensation current: EQU I.sub.COMP .varies.[I.sub.PUMP *F.sub.REF ]/[F.sub.VCO * F.sub.MOD ].(3)
Consequently, the operation of the pump producing the compensation current depends on the reference frequency F.sub.REF, and on the frequency F.sub.VCO of the VCO's output signal.